Recently, as digital technology has been developed, the performance of various electronic units has been further enhanced to catch up with a steep rise in the amount of data to be processed or stored at a time. As a result, semiconductor devices used for those electronic units and semiconductor elements mounted on the semiconductor devices have been rapidly downsized. Correspondingly, to integrate a dynamic RAM (Random Access Memory) more densely, a technique of using a material with a high dielectric constant (which will be herein referred to as a “high-κ material”), instead of silicon oxide or silicon nitride widely used, for a capacitive insulating film of a capacitor has been broadly researched and developed. Further, to implement a novel nonvolatile RAM that can operate at a low operating voltage and write and read data at a high speed, a ferroelectric film with spontaneous polarization properties has been vigorously researched and developed. It is noted that each of the high-κ material and the ferroelectric is an insulating metal oxide.
The most essential task in fabricating a semiconductor memory device such as a nonvolatile RAM is to develop a fabrication process for integrating a capacitor in a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit without deteriorating characteristics of the capacitor. In developing such a fabrication process, it is the most difficult task to suppress reduction of a capacitive insulating film caused by hydrogen or moisture generated during the fabrication process, i.e., to suppress deterioration of capacitor characteristics resulting from reduction of a high-κ material or a ferroelectric.
If capacitor characteristics are deteriorated due to reduction of a capacitive insulating film before an interconnect layer is formed, the capacitive insulating film is re-oxidized during an annealing process performed at high temperatures of 650° C. or higher in an oxygen ambient (which will be hereinafter referred to as a “high-temperature oxygen annealing”), thereby recovering the capacitor characteristics. On the other hand, after the interconnect layer has been formed, the annealing temperature is limited up to about 450° C. because there is a limit on the heat resistance of materials used for interconnection such as aluminum. Thus, an oxidation process with the high-temperature oxygen annealing cannot be used. Accordingly, to suppress the deterioration in capacitor characteristics by preventing reduction of the capacitive insulating film caused by hydrogen or moisture generated after the formation of the interconnect layer, it is necessary to prevent the hydrogen or the moisture from reaching an insulating metal oxide that constitutes the capacitive insulating film.
Hereinafter, a conventional semiconductor device, specifically the semiconductor device disclosed in Japanese Laid-Open Publication No. 10-321811 will be described with reference to the drawings.
FIG. 10 is a cross-sectional view of a conventional semiconductor device.
As shown in FIG. 10, a gate electrode 104 is formed over a region surrounded by an isolating insulating film 102 (which will be hereinafter referred to as a “transistor region”) in a semiconductor substrate 101 with a gate insulating film 103 interposed therebetween. A sidewall 105 is formed on side faces of the gate electrode 104. A doped layer 106 to be source/drain regions is defined in the transistor region of the semiconductor substrate 101.
A first passivation film 107 is deposited to cover the entire surface of the semiconductor substrate 101 where transistors, each including the gate electrode 104, the doped layer 106, and so on, are integrated. On the first passivation film 107, a capacitor 111 made up of lower electrode 108, capacitive insulating film 109 of Pb (Zr1−xTix)O3 (where 0≦x≦1) and upper electrode 110 is formed. A second passivation film 112 is deposited over the first passivation film 107 to cover the capacitor 111. A first contact hole 113A is formed in the second passivation film 112 to reach the upper electrode 110. A second contact hole 113B is formed in the first and second passivation films 107 and 112 to reach the doped layer 106. An interconnect layer 114 is deposited on the second passivation film 112 including the first and second contact holes 113A and 113B. Specifically, parts of the interconnect layer 114 are buried in the first and second contact holes 113A and 113B, thereby electrically connecting the capacitor 111 and the transistor (specifically, the doped layer 106 to be source/drain regions). A third passivation film 115 is deposited on the second passivation film 112 to cover the interconnect layer 114.
A plurality of third contact holes 116 are formed in the first, second and third passivation films 107, 112 and 115 to reach the doped layer 106. A first-layer wire 117 is formed on the third passivation film 115 including the third contact holes 116. Specifically, each of the third contact holes 116 is filled with part of the first-layer wire 117, thereby electrically connecting the first-layer wire 117 and the transistor.
A first interlevel dielectric film 118 is deposited over the entire semiconductor substrate 101 including the first-layer wire 117. The first interlevel dielectric film 118 is, for example, a silicon oxide film deposited by a plasma-enhanced CVD (Chemical Vapor Deposition) process or an SOG (spin-on-grass) film formed by an SOG process. The surface of the first interlevel dielectric film 118 has been planarized. A hydrogen barrier layer 119 is formed over the first interlevel dielectric film 118 to prevent hydrogen or moisture from diffusing, and the entire surface of the hydrogen barrier layer 119 is covered with a second interlevel dielectric film 120. A via hole 121 is formed in the second interlevel dielectric film 120, the hydrogen barrier layer 119 and the first interlevel dielectric film 118 to reach a predetermined area of the first-layer wire 117. The via hole 121 is formed by etching the second interlevel dielectric film 120, the hydrogen barrier layer 119 and the first interlevel dielectric film 118 in that order. A second-layer wire 122 is formed on the second interlevel dielectric film 120 as well as in the via hole 121. In other words, the via hole 121 is filled with part of the second-layer wire 122, thereby electrically connecting the first-layer wire 117 and the second-layer wire 122.
In the conventional semiconductor device shown in FIG. 10, the second interlevel dielectric film 120 is deposited over the first interlevel dielectric film 118 on the first-layer wire 117, with the hydrogen barrier layer 119 interposed between the first and second interlevel dielectric films 118 and 120. Thus, it is possible to suppress the reduction of the capacitive insulating film 109 caused by hydrogen or moisture generated after the deposition of the second interlevel dielectric film 120.
However, the present inventors found that the conventional semiconductor device shown in FIG. 10 has the following two problems. A first problem is that the capacitive insulating film 109 is reduced by hydrogen generated during the deposition of the first interlevel dielectric film 118, resulting in deteriorating characteristics of the capacitor 111. A second problem is that moisture contained in the first interlevel dielectric film 118 is diffused with the passage of time to reach the capacitor 111 after the first interlevel dielectric film 118 has been deposited, resulting in deteriorating characteristics of the capacitor 111. Since the first-layer wire 117 is formed under the first interlevel dielectric film 118, it is impossible to recover characteristics of the capacitor 111 through an oxidation process using the high-temperature oxygen annealing after the first interlevel dielectric film 118 has been deposited.
FIGS. 11(a) and 11(b) are views for use in describing the first and second problems.
If a silicon oxide film 118A deposited by a plasma-enhanced CVD process, for example, is used as the first interlevel dielectric film 118, silane or tetraethylortho silicate (TEOS) containing hydrogen, for example, is used for the silicon oxide film 118A. Thus, as shown in FIG. 11(a), hydrogen ions or hydrogen radicals that have been generated in large quantity in a plasma reach the capacitor 111. As a result, the high-κ material or ferroelectric used for the capacitive insulating film 109 is reduced, thus deteriorating characteristics of the capacitor 111.
In addition, if a silicon oxide film 118B formed by an SOG process or by reaction of ozone and TEOS, for example, is used as the first interlevel dielectric film 118, the silicon oxide film 118B contains a large amount of moisture, i.e., OH radicals, and these OH radicals reach the capacitor 111 one after another with the passage of time as shown in FIG. 11(b). As a result, the high-κ material or the ferroelectric used for the capacitive insulating film 109 is reduced, thus deteriorating characteristics of the capacitor 111. In addition to the OH radicals that reach the capacitor 111 due to the above-described change over time, other OH radicals also reach the capacitor 111 easily when a heat process is performed at temperatures of 400° C. or higher after the deposition of the first interlevel dielectric film 118, thus deteriorating characteristics of the capacitor 111.
That is to say, in the conventional semiconductor device, it is impossible to prevent the capacitor characteristics from deteriorating due to reduction of the capacitive insulating film made of an insulating metal oxide, and thus excellent characteristics cannot be obtained.